Conventional electrically erasable and programmable (EEPROM) memory devices are known, and include source and drain regions laterally spaced from one another in a substrate. These memory devices also include an electrically isolated or floating gate spaced from a portion of the substrate between the source and drain regions by an insulating layer. A programming gate is then formed over the floating gate.
Upon application of appropriate biases to the programming gate, as well as the source and drain regions, charges are selectively induced onto the floating gate, thereby programming the EEPROM memory device. In the presence of such charge, current may be inhibited from flowing between the source and drain regions, while the absence of charge may permit current flow. By detecting the presence of absence of current flowing through the EEPROM memory cell, a high ‘1’ bit or low ‘0’ bit, for example, can be read or sensed by known external circuitry.
In order to increase device density and improve memory capacity, there has been a trend in the art to make EEPROM memory devices smaller, such that dimensions of each structure in the device, including the floating gate, are preferably reduced. Reducing the channel length of the device, however, may induce punch through breakdown during programming operations, because a high source voltage, e.g., in excess of 4.5 V, is typically applied during such operations
In addition, in conventional EEPROM cells, having either a split or stacked gate structure, charge in the channel can travel substantially linearly between the source and drain. During programming using either Source Side Hot Electron (“SSHE”) injection or Channel Hot Electron (“CHE”) injection, the momentum and the travel direction of the charge must be changed so that a sufficient amount of charge is injected into the floating gate instead of flowing to the drain. The channel length of the floating gate, however, is relatively short (>0.1 um), and, thus, with voltages typically applied to the memory cell during programming, the resulting change in momentum and travel direction of the charge may be insufficient to direct enough charge to the floating gate to adequately program the device. As a result, relatively low programming efficiencies are obtained (e.g. <1E-6 for CHE). Such low programming efficiency is likely to be found in devices having a planar structure (i.e., not formed in a groove or trench). High voltages are often required in order to keep programming efficiency in scaled memory cells having floating gates with shorter channel lengths. Such high voltages, however, prevent the scale down of channel length and result in the high power consumption.
In an article to Lee et al. (“Vertical Floating-Gate 4.5 F2 Split-Gate NOR Flash Memory at 110 nm NODE,” 2004 SYMPOSIUM ON VLSI TECHNOLOGY, PP. 72-73.), a split gate cell structure is described having a vertical floating gate channel provided in a trench formed in a substrate. As a result, the planar area occupied by this device on the surface of the substrate was reduced. Also, programming efficiency was increased by using ballistic injection. However, the device disclosed in the Lee article requires a large common source voltage to provide an adequate coupling voltage to the floating gate and a sufficient potential drop for ballistic injection. It appears to the inventors of the present application that the device disclosed in Lee et al. may also suffer from punch through, which may limit scalability of the word line channel.
The present invention is directed toward overcoming one or more of the shortcomings in the prior art.